On a VLSI integrated circuit, such as a microprocessor, some signal lines may be routed adjacent to each other over relatively large distances. This may be necessary because the signals have a common source and destination; are part of a large multi-bit bus, or were coincidentally routed adjacent to each other by an automated router. Unfortunately, this arrangement causes problems that may lead to unreliable, or incorrect, functioning of the integrated circuit.
When at least one of the signal lines switches (the culprit) while at least one of the other signals is attempting to remain at its previous value (the victim), the capacitance between the switching line (or lines) will cause the victim line to "glitch" as charge is capacitively transferred between the culprit line(s) and the victim line. This "glitch" can cause failures when, for example, it causes the victim line to rise above a gate threshold voltage from ground, turning on an n-channel FET (field effect transistor) whose gate is connected to the victim line.
One solution to this problem is to increase the spacing between signal lines. This reduces the amount of charge coupled from the culprit(s) to the victim by decreasing the capacitance between them. However, this is undesirable because it increases the cost of the integrated circuit by reducing the overall density of the VLSI integrated circuit.
Another solution is to add a "ballast" capacitor connected between the victim signal and a power supply. This reduces the amount of "glitch" voltage change that occurs by increasing the overall capacitance of the victim line. However, this is undesirable because the "ballast" capacitor burdens the victim line with extra charge that must be removed from the victim line when the victim line switches even though some of that charge is not used to prevent "glitching."
Thus, the need has arisen for an improved way of reducing "glitch" due to capacitive coupling between signal lines on an integrated circuit. The improved "glitch" reduction scheme should not require increased line spacing so that the overall density of the integrated circuit (and hence, the cost) is not significantly impacted. Furthermore, such an improved scheme should minimize the amount of capacitance added to the victim line so that the victim line may still switch a rapidly as possible thus maximizing the speed of the circuit.